1. Field of the Invention
The present invention relates to a semiconductor device for outputting a signal externally and more particularly, to an output circuit for outputting data in a semiconductor device. Specifically, the invention relates to the configuration of a data output circuit capable of adjusting data output speed so as to output data at high speed without causing ringing. More specifically, the invention relates to a semiconductor device capable of switching a slew rate between a normal mode and a slow slew rate mode slower than the normal mode.
2. Description of the Background Art
As an example of a semiconductor circuit device operating synchronously with an external clock signal, there is a clock synchronous memory. In the clock synchronous memory, data is input and output synchronously with a clock signal. A data transfer speed can be therefore determined by an external clock signal, and high-speed data transfer can be achieved.
In such a clock synchronous memory, in order to drive an external load at high speed for outputting data synchronously with a clock signal, an output buffer circuit is provided.
FIG. 18 is a diagram showing an example of the configuration of a conventional output buffer circuit. In FIG. 18, the output buffer circuit includes: a P-channel MIS (insulated gate type field effect) transistor PQ connected between a power supply node and an output node DN, and receiving internal read data VO at a gate thereof; and an N-channel MIS transistor NQ connected between output node DN and a ground node, and receiving internal read data VO at a gate thereof. To the output buffer circuit, in order to suppress an influence on an internal circuit in data output operation, a power supply voltage VDDQ dedicated to the data output is applied. Internal read data VO is therefore a signal having an amplitude of the level of power supply voltage VDDQ. Generally, output power supply voltage VDDQ is a power supply voltage higher than an internal power supply voltage and the level converting (from the internal power supply voltage level to the output dedicated power supply voltage on an internal data) is performed to generate the internal read data VO.
When internal read data VO is at an H level (logical high level), N-channel MIS transistor NQ is in an ON state, and P-channel MIS transistor PQ is in an OFF state. Output node DN is discharged to the ground voltage level, and output data DQ attains an L level (Logical low level).
When internal read data VO is at the L level, P-channel MIS transistor PQ is in the ON state and N-channel MIS transistor NQ is in the OFF state. In this state, output node DN is driven to the output power supply voltage VDDQ level, and output data DQ attains the H level.
By using the output buffer circuit as shown in FIG. 18, the external load on output node DN is driven at high speed and data is output at high speed.
The output driving capability (slew rate) of a conventional output buffer circuit is optimally designed so as not to cause ringing in an output signal. Usually, the slew rate is adjusted by controlling the current supplying capability of a MIS transistor for driving an output node. In a clock synchronous memory such as an SDRAM (synchronous dynamic random access memory), the frequency of a clock signal is designated according to the application. Therefore, the output driving capability (slew rate) of the output buffer circuit is also set as a default value.
In the manufacturing stage, the slew rate is trimmed (finely tuned) so as to satisfy the default value. When the external clock signal is a clock signal in the range specified as a default value, the output node can be driven at high speed according to the external clock signal, without causing ringing.
However, when an output load is unchanged even where the frequency of the external clock signal is decreased, although an output data signal can be generated without causing ringing, since the output buffer circuit operates at a higher speed than need be, such a problem occurs that a current is unnecessarily consumed.
Even if the external clock signal is a clock signal corresponding to the default value, when the external load connected to the output node of the output buffer circuit becomes lighter depending on an application, the output node is equivalently driven by a greater current driving capability, and it consequently causes a problem of occurrence of ringing. Generally, as the external load, the minimum external load is set as a specification value. Therefore, when the output load lighter than the specification value is connected, the slew rate of the output buffer circuit is not adjusted from the viewpoint of a simplification of the circuit configuration.
Conventionally, the output node is usually driven by an output driving capability optimally set as a default value. The slew rate is not conventionally adjusted by setting the output driving capability (slew rate) to be smaller than the default value in the normal mode.
Japanese Patent Laying-Open No. 11-213665(1999) discloses a configuration of detecting the frequency of a clock signal and setting the number of output driving transistors in accordance with the detected clock signal frequency in order to adjust the slew rate in accordance with the clock frequency. In the prior art, in order to address an increase in the frequency of an external clock signal in association with technical development, the slew rate can only be set to be higher than the default value by selectively increasing the number of output transistors but can not be set to be lower than the default value. Consequently, the prior art has a problem that its application is limited.
In the case of adjusting the output driving capability of the output buffer circuit, when the slew rate is set to be low, speed in change of an output signal becomes slow. From a viewpoint of a high speed operation of the whole system, however, a signal has to be driven to a definite state at a timing as fast as possible. In the conventional slew rate adjustment, only the output driving capability of the transistor is adjusted, but the signal output timing is not adjusted.
In the adjustment of the slew rate, in order to adjust the driving capability of a pull-up output transistor for driving an output node to the H level or a pull-down output transistor for driving an output node to the L level in an output buffer circuit, an adjusting transistor of the same conductivity type as that of the output transistor is employed and is selectively set in an ON state. The step of adjusting the slew rate is therefore determined by an adjusting step of the driving capability of the adjusting transistor of the same conductivity type, and there is a problem that the slew rate adjustment width can not be narrowed.
Particularly, in the case of decreasing the slew rate by using the transistor of the same conductivity type as a slew rate adjusting transistor, the timing of definition of an output signal is delayed. Consequently, a problem that the output data signal cannot be transferred at high speed without causing ringing occurs.
In a normal output circuit, as the transistors for driving an output node in the same direction independently of slew rate adjustment, the transistors of the same conductivity type are used. This is because a circuit occupying area is increased due to necessity of a well isolation region if the transistors of opposite conductivity type are used. In the case of using a P-channel MIS transistor (insulated gate field effect transistor), the current driving capability is smaller than that of an N-channel MIS transistor. In order to obtain a necessary current driving capability, the size (ratio of channel length and channel width) of the P-channel MIS transistor is set to be large, and such a problem arises that the circuit occupying area increases.
Such a problem of the output buffer circuit similarly occurs not only in the above-described clock synchronous memory but also in an output circuit of a normal semiconductor integrated circuit device.
An object of the invention is to provide a semiconductor device capable of setting an output driving capability to be smaller than a default value for adjusting a slew rate.
Another object of the invention is to provide a semiconductor device capable of adjusting a slew rate without changing the definition timing of an output signal.
Further object of the invention is to provide a semiconductor device capable of accurately adjusting a slew rate while suppressing an increase of a circuit occupying area as much as possible.
Further another object of the invention is to provide a semiconductor device capable of pulling up an output signal at high speed without increasing a circuit occupying area.
A semiconductor device according to a first aspect of the invention includes: a plurality of transistors connected in parallel to an output node; a register circuit for storing data for setting an operation state of each of the transistors; and an output driving circuit for driving the plurality of transistors in accordance with an internal signal. In the register circuit, either a default value for designating a driving capability of the output node in a normal mode or data for designating a slow slew rate mode for designating a driving capability smaller than that in the normal mode is stored. The output driving circuit drives the plurality of transistors selectively in accordance with the internal signal based on data stored in the register circuit.
A semiconductor device according to a second aspect of the invention includes first and second insulated gate field effect output transistors of different conductivity types from each other connected between a power source node and an output node. The first and second output transistors drive the output node in the same direction in accordance with an output control signal. The first output transistor is formed in a semiconductor substrate region of a first conductivity type, and the second output transistor is formed in a semiconductor substrate region of a second conductivity type formed, in the first substrate region, being surrounded by the first semiconductor substrate region.
A semiconductor device according to a third aspect of the invention includes: a level converting circuit, receiving an external power supply voltage as an operation power supply voltage, for converting a level of an internal output signal having a first amplitude to convert an amplitude of the internal output signal; a driving circuit receiving the external power supply voltage as an operation power supply voltage and generating an output control signal in accordance with an output signal of the level converting circuit; an output transistor for driving an output node to the external power supply voltage level in accordance with the output control signal from the driving circuit; and a reset transistor for driving an output node of the level converting circuit to a voltage level at which the output transistor is turned off in accordance with a voltage level of an external power supply node receiving the external power supply voltage.
By changing the default value stored in the register circuit, the number of transistors for driving the output node can be changed, and the driving capability of the output node, or the slew rate can be set to be smaller than the default value.
By making the conductivity types of the transistors driving the output in the same direction when conductive, different from each other and forming the substrate region for forming the transistor of one conductivity type in the semiconductor substrate region for forming the transistor of the other conductivity type, a region for isolating the transistor forming regions becomes unnecessary, so that the circuit occupying area can be reduced. By using the transistors of different conductivity types, the driving capability of the transistor for driving the output node can be efficiently adjusted. Thus, with a small circuit occupying area, the output node can be driven at high speed.
When the output transistor drives the output node in accordance with a level-converted signal, by setting the voltage level of the output node of the level converting circuit to a voltage level at which the output transistor is turned off in accordance with the power supply voltage level, the output transistor can be turned off reliability irrespective of a power up sequence and a power down sequence. Thus, a power consumed at the time of turning up and down the power supply can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.